On October 19, at the 2026 RISC-V China Summit in Shenzhen, ZTE Microelectronics officially unveiled its first high-performance RISC-V CPU for AI computing centers, the "Everest 200." Specific specs were not disclosed; a formal launch is expected by year-end.
The Everest 200 is based on the RVA23 standard, supporting Hypervisor, AIA, CoVE, and RVV 1.0 vector extensions. RVA23 is the key baseline for RISC-V entering application processor and server markets, and supporting it ensures basic software ecosystem compatibility; AIA advanced interrupt architecture and Hypervisor are critical for server virtualization and cloud-native scenarios. The core uses a 64-bit superscalar out-of-order architecture with wide decode, advanced branch prediction, and deterministic real-time execution.
On AI, the Everest 200 integrates high-performance Vector and Matrix compute units, with hardware acceleration for RAG retrieval and reranking, claiming it can run hundred-billion-parameter MoE models. Memory supports the highest DDR5 standard, DDR MRDIMM, and large-capacity expansion; MRDIMM, a new-gen high-bandwidth memory module, suits bandwidth-sensitive AI inference. Interfaces support PCIe 6.0 and CXL 3—CXL 3 being key for memory expansion and pooling, letting CPU-side memory act as an overflow area for large models when GPU memory is insufficient, especially valuable for long-context inference. Energy efficiency emphasizes lower power, higher efficiency, and better TCO.
Shi Yijun, GM of ZTE Microelectronics' wireless and compute business, said the Everest 200 targets three applications. Agent CPU clusters stress RISC-V instruction-level acceleration to boost agent execution efficiency, as agent workloads involve many lightweight, concurrent task scheduling and tool calls requiring low-latency response under high concurrency. In inference super node host CPU scenarios, the Everest 200 serves as host CPU for GPU and accelerator clusters, running small and medium LLM inference with instruction-level acceleration for KV Cache—a major source of memory usage in large-model inference; optimizing its management and movement at the CPU level directly affects inference economics and usable context length. In enterprise AI computing hybrid inference, it supports RISC-V native AI with XPU accelerator all-in-one schemes, where cold experts in MoE architectures run on CPU and hot experts on GPU or accelerators—a practical path to lowering AI computing center TCO.
ICgoodFind Summary: The Everest 200 packs RVA23, Vector/Matrix acceleration, CXL 3, and MRDIMM into one RISC-V CPU for AI computing centers, targeting a CPU-GPU division of labor in inference. Sinking MoE cold experts to CPU and optimizing KV Cache on the CPU side point to one goal: finding structural space to cut inference costs beyond GPUs.
