Intel CTO Pushkar Ranade, in an interview video released October 22, said Intel's process technology gap with TSMC has narrowed to a few percentage points, but catching up to TSMC's manufacturing scale will be a slow process. He stressed that on-time process execution, yield improvement, and rapid capacity expansion matter more than a small lead in performance or die area density.
Ranade noted TSMC's current wafer manufacturing scale is clearly larger than Intel's, and competition involves not just technical metrics but the ability to stably produce large volumes of advanced chips. On technology level alone, Intel is close to TSMC, though gaps of a few percentage points may remain in performance, power, and area density. He argued that advanced-node competition cannot rely on single benchmark results—when a process lags a full generation, the gap is obvious, but when technologies are close, manufacturing execution, yield, and capacity ramp speed matter more. Even with a few percentage points of difference, on-time process progress and high yields still offer room to gain ground.
Capacity expansion constraints were also noted. Ranade said even if Intel wanted to sharply raise advanced-node wafer output, global semiconductor equipment supply could not support 10x capacity growth; doubling output is more feasible. EUV lithography is a major bottleneck, with other equipment also tight. Moving from 18A to 14A, Intel expects to reuse about 80% of equipment, but new processes still need some new tools, with lead times of about 18 months; building new fabs could delay production further.
Chris Aus, VP and GM of Intel's Manufacturing Development and Customer Collaboration, discussed High-NA EUV. He said Intel's backside power delivery moves the power network to the wafer backside, reducing frontside wiring pitch pressure, allowing direct use of High-NA EUV in some process layers. Traditionally, power and signal lines both occupy frontside space; backside power frees space for transistors and signal interconnects, relaxing pitch requirements so some patterns can be made with single High-NA EUV exposure. Aus believes Intel and TSMC's different technical architectures lead to different conclusions on High-NA EUV economics; in some designs, TSMC needs tighter pitches and still requires double patterning.
Intel's 14A process offers High-NA EUV as an optional PDK solution, discussed case by case with customers rather than mandated for all.
ICgoodFind Summary: Intel's CTO narrows the process gap to a few percentage points but admits capacity catch-up is the slower variable. With 18-month equipment lead times and constrained EUV supply, once process technology nears parity, manufacturing scale and yield ramp become the real threshold for foundry competitiveness.
