Tesla has outlined its AI accelerator roadmap, detailing chip development over the coming years. The sixth-generation inference accelerator SI6 is expected in 2029–2030 with 80x the compute performance of the current fourth-generation chip and significantly more memory. The revived third-generation Dojo D3 training accelerator will shift to a multi-die design combining 2.5D and 3D packaging with stacked HBM, abandoning the SRAM-centric architecture of the first two generations. Tesla has also begun calling its new accelerators "Super Intelligence" and renaming the chips as the SI series.
Dojo D3 returns with a very different design. Musk cancelled the entire wafer-scale Dojo project in August 2025, and in August 2026 said SpaceX and xAI would use Nvidia hardware across ground and space data centers. The new roadmap shows Tesla still plans D3, but with a multi-die architecture integrating 2.5D and 3D packaging and stacked HBM, a clear departure from the first-generation Dojo D1's wafer-scale system integration. D1 interconnected 25 D1 processors via wafer-level packaging with 11GB of SRAM, relying on distributed on-chip memory. The move to HBM signals Tesla's intent to greatly expand memory capacity as AI models grow and parameters, activations, and intermediate data demand more storage. Whether Tesla fully abandons wafer-scale integration is unclear; custom HBM could theoretically stack on logic dies interconnected via wafer-level packaging, but that raises thermal, manufacturing, yield, and long-term reliability challenges. D3 will be optimized for space, training, and scale-out, and for deployment in outer space, suggesting at least some variants will use radiation-hardened designs.
SI6 will deliver 80x the compute of HW4 and 9x the memory. Depending on how HW4 performance is estimated, SI6 could range from 17,280 to 46,080 TOPS. Nvidia's Rubin GPU offers 50 NVFP4 PFLOPS inference performance, but Rubin is already shipping while SI6 arrives in 2029–2030. Tesla's current fourth-generation inference processor, originally HW4, then AI4, is now SI4, built by Samsung Foundry on a 7nm-class process with traditional FCBGA packaging and an estimated 16GB of GDDR6.
Before SI6, Tesla expects to launch the fifth-generation SI5, produced by TSMC and Samsung on 3nm-class and 2nm-class processes with a multi-chip module design. Tesla expects SI5 to deliver 40x HW4 performance, with power between 250 and 800W and 96GB memory, 6x the previous generation. SI6 will use a 2nm-class process under a Samsung Foundry agreement running through 2033. Given the 2029–2030 timeline, relevant nodes may include automotive-grade SF2A, performance-enhanced SF2P, or SF2Z with backside power delivery. SI6 will continue the multi-chip module design to control packaging cost. Tesla has not set a timeline for bringing HBM to inference accelerators, and SI6 may not adopt it.
ICgoodFind Summary: Dojo D3's shift from SRAM to HBM and SI6's 80x target on 2nm point to the same trend: as AI models scale, memory capacity is becoming the core constraint on accelerator architecture. D3's radiation-hardened design for space shows Tesla's chip planning now extends beyond vehicles to more complex deployment scenarios.
