Aug 27 – At the just-concluded Hot Chips 2025, Japan’s Rapidus announced it completed tape-out of 2nm GAA (Gate-All-Around) test chips (a milestone actually hit on July 10). It plans to start large-scale 2nm mass production in 2027, with its IIM-1 factory expected to reach 25,000 wafers/month capacity.
Rapidus’ 2nm chips use ASML’s EUV lithography, and the node now meets all preset electrical performance indicators—laying a solid mass production foundation.
At the conference, Rapidus outlined IIM-1’s goals and its flexible production edge for differentiation (vs. TSMC/Intel, which will lead by 1-2 nodes in 2027):
- Single-wafer process: 50-day design-to-wafer cycle (vs. ~120 days for traditional hybrid processes), enabling early anomaly detection and efficiency gains.
- 15-day fast delivery: Far shorter than the 50-day industry standard for 2nm wafers, meeting urgent customer needs.
This model relies on customized backend processes and integration of OSAT, EDA, IP, R&D, and material supply chain resources.
Rapidus has advanced IIM-1 quickly: groundbreaking in Sept 2023, with over 200 advanced tools installed/connected by June 2025.
Still, semiconductor manufacturing is volatile. While Rapidus’ vision has credibility, its execution will determine if it can deliver mass production and gain market foothold.
ICgoodFind: We’ll keep tracking Rapidus for the latest semiconductor updates.
