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Description Clock generator, 1.47456GHz, 1.71V to 3.47V, 12 outputs, QFN-64
Product QR code
Packaging QFN-64
Delivery time
Packaging method Tray
Standard packaging quantity 1
15.35  yuan 15.35yuan
5+:
$ 17.9618
50+:
$ 17.1942
200+:
$ 16.7644
500+:
$ 16.6569
1000+:
$ 16.5495
2500+:
$ 16.4266
5000+:
$ 16.3499
7500+:
$ 16.2731
Quantity
5+
50+
200+
500+
1000+
Price
$17.9618
$17.1942
$16.7644
$16.6569
$16.5495
Price $ 17.9618 $ 17.1942 $ 16.7644 $ 16.6569 $ 16.5495
Start batch production 5+ 50+ 200+ 500+ 1000+
  • Freight charges   In stock Freight rate:$13.00
  • Quantity
    Inventory(4688) Minimum order quantity(5)
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Technical parameters/frequency: 1.47456 GHz

Technical parameters/number of output interfaces: 12

Technical parameters/number of circuits: 1

Technical parameters/number of pins: 64

Technical parameters/dissipated power: 1.6 W

Technical parameters/duty cycle: 60% (Max)

Technical parameters/operating temperature (Max): 85 ℃

Technical parameters/operating temperature (Min): -40 ℃

Technical parameters/dissipated power (Max): 1600 mW

Technical parameters/power supply voltage: 1.71V ~ 3.47V

Technical parameters/power supply voltage (Max): 3.47 V

Technical parameters/power supply voltage (Min): 1.71 V

Encapsulation parameters/installation method: Surface Mount

Package parameters/number of pins: 64

Encapsulation parameters/Encapsulation: QFN-64

External dimensions/height: 0.83 mm

External dimensions/packaging: QFN-64

Physical parameters/operating temperature: -40℃ ~ 85℃

Other/Product Lifecycle: Active

Other/Packaging Methods: Tray

Compliant with standards/RoHS standards: RoHS Compliant

Compliant with standards/lead standards: Lead Free

Customs information/ECCN code: EAR99

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Alternative material

Model Brand Similarity Encapsulation Introduction Data manual
SI5380A-B-GM SI5380A-B-GM Silicon Labs 类似代替 QFN-64
Si5380 无线抖动衰减时钟倍增器 The Si5380 is a single chip Ultra Low Jitter, Any Frequency, 12-output JESD204B Clock Generator for 4G/LTE RRU. Integrated DSPLL technology simplifies design and PCB footprint together with removing the need for external VCXO, loop filter components and complex external filtering. Low phase noise JESD204B clock with interated LC-VCO. Highly immune to switching power supply noise and other noise sources. Simple and intuitive configuration with the ClockBuilder Pro software from Silicon Labs. Supported by the Si5380 Development Kit (RS 8807317) \- 支持 JESD204B 定时:DCLK 和 SYSREF \- 输入频率范围:10 MHz – 750 MHz \- 输出频率范围:480 kHz – 1.47456 GHz \- 极佳的抖动性能:80 fs typ (12 kHz – 20 MHz) \- 相位噪声地板:–159 dBc/Hz \- 正齿性能:最大 –103 dBc((122.88 MHz 载频) \- 高度可配置输出,与 LVDS、LVPECL、LVCMOS、HCSL 和 CML 兼容,带可编程信号振幅 \- 4 输入、12 输出、64 引脚 QFN \- 温度范围:–40 至 +85 °C ### 时钟发生器/缓冲器
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