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Model CY7C12501KV18-400BZC
Description 36Megabit DDR II+SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) 36 Mbit DDR II+SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
Product QR code
Brand: Cypress Semiconductor
Packaging FBGA-165
Delivery time
Packaging method Tray
Standard packaging quantity 1
104.52  yuan 104.52yuan
1+:
$ 120.1992
10+:
$ 117.0635
50+:
$ 114.6595
100+:
$ 113.8234
200+:
$ 113.1962
500+:
$ 112.3601
1000+:
$ 111.8375
2000+:
$ 111.3149
Quantity
1+
10+
50+
100+
200+
Price
$120.1992
$117.0635
$114.6595
$113.8234
$113.1962
Price $ 120.1992 $ 117.0635 $ 114.6595 $ 113.8234 $ 113.1962
Start batch production 1+ 10+ 50+ 100+ 200+
Check the distribution price
  • Freight charges：   In stock Freight rate：$13.00
  • Quantity： Inventory(3772) Minimum order quantity(1)
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Technical parameters/access time: 0.45 ns

Technical parameters/operating temperature (Max): 70 ℃

Technical parameters/operating temperature (Min): 0 ℃

Technical parameters/power supply voltage: 1.7V ~ 1.9V

Encapsulation parameters/installation method: Surface Mount

Package parameters/number of pins: 165

Encapsulation parameters/Encapsulation: FBGA-165

External dimensions/packaging: FBGA-165

Physical parameters/operating temperature: 0℃ ~ 70℃

Other/Product Lifecycle: Unknown

Other/Packaging Methods: Tray

Compliant with standards/RoHS standards:

Compliant with standards/lead standards: lead-free

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Alternative material

Model Brand Similarity Encapsulation Introduction Data manual
CY7C12501KV18-400BZC CY7C12501KV18-400BZC Cypress Semiconductor 类似代替 FBGA-165
36兆位的DDR II + SRAM 2字突发架构（ 2.0周期读延迟） 36-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
PDF
CY7C12501KV18-400BZXC CY7C12501KV18-400BZXC Cypress Semiconductor 完全替代 FBGA-165
SRAM Chip Sync Single 1.8V 36M-Bit 1M x 36 0.45ns 165Pin FBGA Tray
PDF

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