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Model CD4051BPW
Description CMOS模拟多路复用器/多路解复用器与逻辑电平转换 CMOS Analog Multiplexers/Demultiplexers with Logic Level Conversion
Product QR code
Brand: TI
Packaging TSSOP-16
Delivery time
Packaging method Tube
Standard packaging quantity 1
1.14  yuan 1.14yuan
  • Freight charges：   In stock Freight rate：$13.00
  • Quantity： Inventory(9644) Minimum order quantity(1)
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Technical parameters/power supply voltage (DC):

7.00 V

 

Technical parameters/number of output interfaces:

1

 

Technical parameters/power supply current:

100 µA

 

Technical parameters/number of circuits:

1

 

Technical parameters/number of channels:

8

 

Technical parameters/digits:

8

 

Technical parameters/transmission delay time:

20.0 ns

 

Technical Parameters/Voltage Wave Node:

5.00 V, 10.0 V, 15.0 V

 

Technical parameters/bandwidth:

20 Mhz

 

Technical parameters/number of inputs:

8

 

Technical parameters/operating temperature (Max):

125 ℃

 

Technical parameters/operating temperature (Min):

-55 ℃

 

Technical parameters/3dB bandwidth:

20 MHz

 

Technical parameters/power supply voltage:

3V ~ 20V

 

Technical parameters/power supply voltage (Max):

18 V

 

Technical parameters/power supply voltage (Min):

5 V

 

Encapsulation parameters/installation method:

Surface Mount

 

Package parameters/number of pins:

16

 

Encapsulation parameters/Encapsulation:

TSSOP-16

 

Dimensions/Length:

5 mm

 

Dimensions/Width:

4.4 mm

 

Dimensions/Height:

1.15 mm

 

Dimensions/Packaging:

TSSOP-16

 

Physical parameters/operating temperature:

-55℃ ~ 125℃

 

Other/Product Lifecycle:

Active

 

Other/Packaging Methods:

Tube

 

Compliant with standards/RoHS standards:

RoHS Compliant

 

Compliant with standards/lead standards:

Lead Free

 

Compliant with the REACH SVHC standard:

No SVHC

 

Compliant with standard/REACH SVHC versi

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Alternative material

Model Brand Similarity Encapsulation Introduction Data manual
CD4051BPWRG4 CD4051BPWRG4 TI 完全替代 TSSOP-16
CMOS模拟多路复用器/多路解复用器与逻辑电平转换 CMOS Analog Multiplexers/Demultiplexers with Logic Level Conversion

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