At its AMD In Depth event in Las Vegas, AMD officially disclosed the Zen 6 architecture and the sixth-gen EPYC processor Venice, built on TSMC's 2nm process. AMD sees Agentic AI as a key driver of the next server CPU growth cycle, forecasting the data center CPU market will grow at over 50% CAGR to about $220 billion by 2030.
AMD believes early AI data center buildout centered on GPUs, with CPUs handling data preparation, task scheduling, and system management. But as AI moves from large-model training and inference to Agentic AI, an agent constantly queries databases, calls APIs, retrieves context, executes code, uses external tools, and coordinates tasks—much of this work does not happen on GPUs but requires continuous CPU involvement. AMD's architecture data shows the chatbot era had a CPU-to-GPU ratio of about 1:4; in the Agentic AI era, it may approach 1:1. AMD cites forecasts of 2.5 billion active agents in production by 2030, nearly 80x today.
AMD offers two core designs: Zen 6 and Zen 6c. Zen 6 targets workloads sensitive to single-core performance, frequency, and latency—versus Zen 5, CCX cores rise from 8 to 12, with up to 12 cores per CCD, L3 cache from 32MB to 48MB, and max frequency from 5.0GHz to 5.3GHz. Zen 6c targets cloud computing and massively parallel workloads, with CCX cores from 16 to 32, L3 cache from 32MB to 128MB, and max frequency from 3.7GHz to 4.1GHz. In fixed-frequency 16-core tests, Zen 6c delivers about 20% geometric mean IPC gain in enterprise and cloud server workloads, about 31% in AI workloads, and about 27% across combined AI and server workloads.
Venice uses a Chiplet design, with a SoC of up to 8 compute chiplets and 2 I/O chiplets. CCDs use TSMC 2nm, with standard Zen 6 CCDs up to 12 cores and Zen 6c at 32 cores. I/O dies use 6nm in a dual-IOD split design, each with 8 DDR5 channels, 16 total, supporting MRDIMM up to 12.8GT/s and up to 1.6TB/s theoretical memory bandwidth per socket. Each IOD has 48 64G SerDes and 8 16G SerDes. Chiplets communicate via Elevated Fanout Bridges for lower energy per bit and latency, with fifth-gen Infinity Fabric.
Venice drops a single-platform strategy for SP7 and SP8 platforms with different physical interfaces, plus 9006X (Venice-X) and 9006 LP (Verano) sub-series. Embedded 9006 SP7 CPUs offer up to 256 cores, 512 threads, 16 DDR5 channels, RDIMM up to 8000MT/s and MRDIMM up to 12800MT/s, up to 96 PCIe Gen 6 lanes, and CXL 3.1. Versus EPYC Embedded 9005, the 9006 series delivers up to 1.8x overall throughput, 1.5x I/O bandwidth, and 2.7x memory bandwidth, targeting semiconductor automated test equipment, enterprise storage, and network firewalls, with a seven-year supply commitment.
At the system level, AMD offers three Helion Agentic Rack configurations for hyperscale data centers, enterprises using existing air-cooled infrastructure, and All-in-One CPU-GPU integrated racks. On software, AMD uses technology from its MEXT acquisition to bring Flash into memory management, moving cold data to Flash and keeping DRAM for active data. AMD says this cuts DRAM usage by 20%–75% by workload, expands effective memory capacity up to 3x, with latency impact under 4%. In an initial 145-server deployment, it expects about 83% cost savings versus all-DRAM, avoiding about $4.9 million in DRAM spending.
Mercury Research's August report shows AMD held 34.5% of the server processor market in Q2, up from 27.3% a year earlier.
ICgoodFind Summary: AMD's bet on Agentic AI as the next server CPU growth driver, with the CPU-to-GPU ratio moving from 1:4 toward 1:1, points to a repricing of the CPU's role in AI infrastructure. Zen 6c's 31% IPC gain in AI workloads and Venice's dual-IOD 1.6TB/s memory bandwidth are the hardware support, while MEXT's Flash-offload software addresses the AI server memory bottleneck from the cost side.
