Cisco introduced the Silicon One G302, a 51.2T top-of-rack switch chip, at OCP Global Summit 2026, alongside a new out-of-band management system and a 400Gb/s per lane pluggable optics module co-designed with Nvidia.
The G302 uses 224G SerDes technology with 256 SerDes lanes supporting NRZ and PAM4 modulation. It delivers 51.2 Tbps full-duplex switching capacity and can build systems with 32 x 1.6 Tbps Ethernet ports. The chip features a fully shared on-chip packet buffer, allowing any input or output port to use the entire buffer to reduce packet loss and PFC events under bursty traffic. It strengthens traffic scheduling, load balancing, and congestion management for GPU-to-GPU data exchange in AI clusters, with support for RDMA and RoCE v2, programmable network processing units, and SONiC. G302 ships to customers by the end of 2026.
Cisco also announced it is the first to deploy a 51.2T system using Silicon One P200 in production at a leading hyperscale data center. Microsoft has begun production deployment on P200-based systems. Alibaba has deployed its Quantum Cat routers at scale on P200 in its eCORE backbone, combining Cisco chips with custom systems and SONiC.
The 102.4T Silicon One G300, launched earlier in 2026, is available for customer trials with first systems already delivered.
In optics, Cisco and Nvidia detailed USFP, a high-density pluggable module with 400Gb/s per lane and up to 12.8Tb/s capacity. The first transceivers use the same form factor as OSFP modules, housing 16 full-duplex channels, scalable to 32 or more. A two-step insertion mechanism engages high-speed contacts only after the module is seated, reducing wear and improving signal integrity. USFP supports up to 100W without dedicated cooling circuits. Bandwidth density is 4x that of 200Gb/s per lane pluggable modules in the same OSFP size, with about 1.3x the energy efficiency. TE Connectivity and Amphenol are developing USFP cages, connectors, and modules.
For out-of-band management, the Cisco 8001 based on Silicon One A100 brings SONiC into management networks in 10G and 1G versions.
ICgoodFind Summary: Cisco pushes 224G SerDes and 51.2T switching to the top of rack while co-developing 400Gb/s per lane USFP optics with Nvidia. The AI cluster bottleneck is shifting from raw compute to interconnect density, and the cadence of switch and optics iteration is accelerating.
