On October 14, IBM and Siemens announced a new research collaboration to advance IBM's nanostack transistor architecture, unveiled in June. The two will combine IBM's semiconductor device innovation with Siemens' capabilities in EDA, process simulation, lithography optimization, and advanced manufacturing software to develop advanced virtual models for nanostack, enabling performance modeling, design optimization, and manufacturing troubleshooting before chips are built.
The nanostack architecture shifts transistors from 2D planar to 3D vertical stacking with staggered placement, fitting more transistors in the same area. At the 7-angstrom node, it can integrate nearly 100 billion transistors in a fingernail-sized area, about double the density of IBM's 2nm test chip from 2021. Each stacked layer can use different material combinations, independently optimizing performance and power. IBM data shows nanostack delivers up to 50% more performance at the same power, or up to 70% lower power at the same performance, versus 2nm. At VLSI 2026, IBM also reported 40% SRAM scaling improvement, directly relevant to high-bandwidth memory for AI workloads.
IBM Research Director Jay Gambetta said the technology is not about making transistors smaller but reinventing how chips are built. IBM VP of Silicon Technology R&D Huiming Bu positioned it as a scalable transistor platform representing a shift from 2D scaling to 3D. Siemens EDA IC group EVP Ankur Gupta noted that pushing scaling into the angstrom era requires tight co-optimization across device physics, EDA design and manufacturing software, and manufacturing.
IBM has said first products based on the technology will take about five years to reach production with partners. The Siemens collaboration is designed to bridge that lab-to-fab gap. EDA tools and process simulation convert device-level physics innovation into manufacturable, verifiable design flows—otherwise 3D stacking complexity is hard to implement in existing manufacturing systems.
ICgoodFind Summary: IBM's nanostack shifts transistors from planar to vertical staggered stacking, while Siemens' EDA and process simulation turn that 3D design into a manufacturable flow. Across the five-year lab-to-fab window, EDA collaboration is the hardest link to bypass.
