September 30 — Chip design service and IP provider GUC announced on the 22nd of this month that its HBM4E PHY and controller IP, built on TSMC's 2nm N2P process, has completed design tape-out and been adopted by a customer's AI ASIC project.
The HBM4E IP delivers 16Gbps data rates, with advantages in power consumption and die area. It is optimized for signal integrity and power integrity, and compatible with CoWoS-S/R/L advanced packaging.
For 3D SoIC architectures, GUC also introduced a face-up HBM4E IP supporting TSMC SoIC-X technology. This version integrates TSV structures for vertical signal and power transmission, enabling complete interconnect paths for complex 3D chip integration.
ICgoodFind: GUC's HBM4E IP lands on TSMC N2P for AI ASICs, paired with CoWoS and SoIC-X advanced packaging to support 3D heterogeneous integration development.
ICgoodFind Summary: GUC's HBM4E IP on TSMC N2P marks a solid step forward for AI ASIC and 3D integration, with CoWoS and SoIC-X readiness giving designers more flexibility.
