Synopsys has announced the successful silicon validation of its LPDDR6 IP on TSMC's N2P process. This achievement provides a critical, verified solution for applications demanding extreme memory bandwidth, such as mobile, edge AI, and high-performance computing (HPC).
The LPDDR6 standard, the latest from JEDEC, introduces a dual-channel architecture and dynamic voltage and frequency scaling for breakthroughs in both performance and power efficiency. By using this pre-validated IP, customers can significantly reduce project risk and accelerate time-to-market. The LPDDR6 IP expands Synopsys's comprehensive portfolio of interface IP for the N2/N2P nodes.
A senior Synopsys executive stated that this milestone solidifies their leadership in advanced-node IP and delivers a production-ready solution, marking the entry of high-bandwidth, low-power memory interfaces into the angstrom era.
ICgoodFind : This collaboration provides a crucial foundation for storage interface innovation in advanced chips, accelerating the adoption of angstrom-era process technology.
